1. Field of the Invention
This invention relates to insulated gate semiconductor devices having self-aligned gates, and more particularly to its fabrication method
2. Prior Arts
Miniaturization of transistors has been accelerated from year to year in order to comply with the requirements for higher operation speed and higher integration density. Self-alignment technique is indispensable together with fine etching technique to accomplish miniaturization of devices. A self-aligned fabrication method of bipolar devices, which is called Super Self-Alignment (SST) method, is disclosed in p.283, Vol.19 of "Electronic Letters" published in 1983 and in Japanese Laid-Open Pat. No.15230/1980. This method achieves a delay time of 30 pico second. "Technical Research Report SSD 84-101 of Telecommunication Society" issued on Dec. 18, 1984 describes a MOS self-alignment fabrication method called "MUSA-MOST". According to these two methods, a gate electrode on a gate insulated film side between a drain and a source in the case of a MOS device, or on a contact hole side between a base and an emitter in the case of a bipolar device can be self-aligned. But the other end (the top end) of the gate electrode can not be self-aligned, which results in overlappings at the top end of a gate electrode and parasitic capacitance as a consequence. This parasitic capacitance impedes a higher operation speed of the device. Moreover, the methods mentioned above cannot be easily applied to a Lightly Doped Drain (LDD) structure in a miniature insulated gate semiconductor device.